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| PRELIMINARY DATA SHEET For information only TS4405P - Single P-Channel 1.8V Specified MicroSURFTM General Description Taiwan Semiconductor's new low cost, state of the art MicroSURFTM lateral MOSFET process technology in chipscale bondwireless packaging minimizes PCB space and RDS(ON) plus provides an ultralow Qg X RDS(ON) figure of merit. Features * -4.9A, -12V RDS(ON) = 50m at -4.5 Volts * -4.4A, -12V RDS(ON) = 70m at -2.5 Volts * -4.0A, -12V RDS(ON) = 90m at -1.8 Volts * Low profile package: less than 0.8mm height when mounted on PCB. * Occupies only 1.21 mm2 of PCB area. Less than 30% of the area of a SC-70. * Excellent thermal characteristics. * Lead free solder bumps available. MicroSURFTM for Load Switching and PA Switch Patent Pending S S D G Bump Side View Absolute Maximum Ratings Symbol Parameter VDSS VGSS ID PD TJ, TSTG TA=25C unless otherwise noted Ratings -12 +8 -4.9 -10 1.5 -55 to +150 Units V V A W C Drain-Source Voltage Gate-Source Voltage Drain Current - Continuous - Pulsed Power Dissipation (Steady State) Operating and Storage Junction Temperature Range Thermal Characteristics RJA RJR RJC Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-Ball Thermal Resistance, Junction-to-Case 1 85 20 1.8 C/W 6/8/03 Rev0 PRELIMINARY DATA SHEET Electrical Characteristics Symbol V(BD)SS IDSS Parameter Drain-Source Breakdow n Voltage Zero Gate Voltage Drain Current Zero Gate Voltage Drain Current TA=25C unless otherwise specified TS4405P Test Condition VGS=0V, ID=-250A VDS=-12V, VGS=0V VDS=-12V, VGS=0V, T=70C VGS=8V, VDS=0V VDS=VGS, ID=-250A VGS=-4.5V, ID=-1A VGS=-2.5V, ID=-1A VGS=-1.8V, ID=-1A VDS=-12V, VG=0V, F=1MHZ VDS=-12V, VG=0V, F=1MHZ VDS=-12V, VG=0V, F=1MHZ VGS=-4.5V, ID=-4A, VDS=-8V VGS=-4.5V, ID=-4A, VDS=-8V VGS=-4.5V, ID=-4A, VDS=-8V IS=-4A, VGS=0V Min Typ Max -11 -1 -5 100 Units V A A nA V IGSS VGS(th) Gate-Body Leakage Gate Threshold Voltage Drain-Source On-State Resistance -0,58 50 70 90 300 200 80 10 2 1 0.7 m m m pF pF pF nC nC nC V rDS(on) Drain-Source On-State Resistance Drain-Source On-State Resistance Ciss Coss Crss Qg Qgs Qgd VSD Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge Gate Source-Charge Gate Drain-Charge Diode Forw ard Voltage 2 6/8/03 Rev0 PRELIMINARY DATA SHEET Dimensional Outline and Pad Layout TS4405P O 0.25mm Solder Mask O ~ 0.35mm S G S 0.50mm D 0.27mm 0.50mm LAND PATTERN RECOMMENDATION D = Drain Pad S = Source Pad G = Gate Pad SILICON 0.80mm MAX 1.10mm 0.30mm 1.10mm 0.50mm 44XXX MARK ON BACKSIDE OF DIE XXX = Date/Lot Traceability Code Bumps are Eutectic solder 63/37 Sn/Pb Bump O 0.37mm 0.50mm 0.30mm 3 6/8/03 Rev0 |
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